An Instruction Set Nobody Owns
RISC-V is not a chip. It is an instruction set architecture — the fundamental specification that tells a processor how to interpret software commands — released under an open licence by the University of California, Berkeley, in 2010. Unlike x86, which Intel controls, or ARM, which the British-American company of the same name licenses to chipmakers, RISC-V can be implemented by anyone without paying a royalty or seeking permission. That legal status has made it unusually attractive to governments and companies that want to design processors without long-term dependence on a foreign IP holder.
In East and South Asia, that attraction has taken on a sharper edge since the tightening of US export controls on advanced semiconductor technology. China, in particular, has accelerated RISC-V investment across state research institutes, university programmes and commercial chip startups. Several Chinese companies — among them Alibaba's chip subsidiary T-Head, which produces the XuanTie processor family — have shipped RISC-V cores in commercial devices. The architecture also underpins chips used in networked devices, industrial controllers and emerging applications in edge computing.
China's Structured Approach
China's engagement with RISC-V reflects both commercial logic and strategic calculation. For embedded and IoT applications — microcontrollers inside appliances, sensors in factory equipment, chips in automotive subsystems — RISC-V competes directly with existing ARM Cortex-M cores on cost and customisability, without the licence terms that come with ARM's agreements. Chinese chip designers report that for standard embedded workloads, RISC-V silicon can now be taped out, manufactured and validated on timelines comparable to equivalent ARM-based designs.
For higher-performance applications, the picture is more complicated. The toolchain ecosystem around RISC-V — the compilers, debuggers, operating system support and developer documentation that collectively determine how quickly engineers can build working software — is less mature than the ARM or x86 equivalents, which have decades of accumulated tooling behind them. Chinese companies working at the performance edge have invested in building out this toolchain infrastructure, contributing to the RISC-V International consortium and developing proprietary extensions that sit atop the open base specification.
India and Japan Take Different Paths
India's RISC-V engagement has been channelled largely through government-backed institutions. The Indian Space Research Organisation and the Centre for Development of Advanced Computing have both published RISC-V core designs. The SHAKTI processor programme at IIT Madras, running since the mid-2010s, has produced a family of open-source RISC-V cores and supplied them to defence and space research agencies — a route that bypasses commercial licence questions entirely.
Japan's approach leans toward industrial partnerships. Renesas, a dominant supplier of microcontrollers to the global automotive and industrial markets, has incorporated RISC-V cores into several product lines. SoftBank's presence in Japan is strong, and the two architectures coexist in Japanese industrial design without the geopolitical overlay that shapes the Chinese conversation. For Japanese chipmakers, RISC-V is primarily a cost and customisation argument rather than a sovereignty one.
What the Toolchain Gap Means in Practice
The maturity gap in RISC-V tooling shows up most clearly in operating system support. Linux runs on RISC-V, and the upstream kernel has supported the architecture since 2017. Android support arrived more recently. But the breadth of validated drivers, the depth of real-time operating system support for safety-critical embedded applications, and the availability of pre-certified middleware stacks — the kind of software infrastructure that automotive and medical device manufacturers require before committing to a chip architecture — still lags ARM's equivalent by several years.
That gap is closing, and the pace of closure has accelerated as more commercial players commit production designs. The RISC-V International membership roster has grown consistently over the past four years, with Chinese, Indian and Japanese firms among the more active contributors to working groups on vector extensions, security and hypervisor specifications.
The Limits of Open
The open licence does not resolve all dependencies. Advanced RISC-V chips still require sophisticated electronic design automation software — tools made primarily by Cadence, Synopsys and Mentor, all US companies subject to export rules — to be designed. Manufacturing at leading-edge nodes remains concentrated at TSMC and Samsung, both subject to their own regulatory constraints. RISC-V addresses the instruction set layer of the technology stack; it does not address the fabrication or software tool layers above and below it.
For China's chip industry, this means RISC-V is one component of a broader self-sufficiency push, not a complete answer. For India and Japan, it is more straightforwardly a design flexibility tool — useful, increasingly mature, and worth the toolchain investment for the right class of product.