Rapidus, the Japanese government-backed chipmaker built from scratch in 2022, says its pilot production line in Chitose, Hokkaido has moved into full-flow testing of 2-nanometer logic wafers, a milestone the company had targeted for the second half of 2026. The line, known internally as IIM-1, began limited operations last year and has since been running end-to-end process trials rather than isolated test steps — the difference between proving individual tools work and proving an entire fab can turn raw wafers into working chips.
The distinction matters because Rapidus has never run a commercial fab before. It was formed by eight companies — Toyota, Sony, NTT, SoftBank, NEC, Denso, Kioxia and Mitsubishi UFJ Financial Group — with initial capital of just ¥7.3 billion, a fraction of what a leading-edge foundry typically costs to build. Tokyo has since covered the gap directly: government subsidies committed to the project have climbed past ¥1.7 trillion (roughly $11 billion) across successive budget rounds, more than 20 times the founders' original stake, according to figures the Ministry of Economy, Trade and Industry has disclosed in its subsidy filings.
A borrowed transistor design, and why that's the plan
Rapidus is not developing 2nm gate-all-around transistor technology from zero. It licensed the core process from IBM, whose Albany, New York research lab has worked on nanosheet transistors since the early 2020s, and it runs joint development work with Belgium's imec for lithography and materials research. The strategy is deliberately unglamorous: rather than compete with TSMC or Samsung on process invention, Rapidus is betting it can compress the usual multi-year gap between a leading-edge node's first demonstration and its first paying customer by skipping straight to a licensed, already-proven transistor architecture.
That approach carries its own risk. A licensed process still has to be transferred, tuned and stabilized on a new fab's specific tool set, and yield — the percentage of chips on a wafer that actually work — tends to start low on any first-generation line regardless of how proven the underlying transistor design is on paper. Rapidus president Atsuyoshi Koike has said publicly that the company expects yields in the pilot phase to trail those of established foundries by a wide margin before mass production begins, and that closing that gap through 2027 is now the central engineering task at Chitose.
Where Rapidus fits next to TSMC, Samsung and Intel
The 2nm race already has three entrenched players. TSMC began volume production of its N2 node in the second half of 2025 at fabs in Hsinchu and Kaohsiung, with Apple and Nvidia reported among the first customers to book capacity. Samsung Foundry has pushed its own 2nm gate-all-around process (SF2) toward broader adoption after early struggles with defect rates. Intel, meanwhile, has staked its foundry turnaround on the 18A node, using it for its own Panther Lake client chips as a proof point before it tries to win outside customers at scale. Rapidus enters this field years behind on manufacturing experience but without the burden of an existing customer base it has to protect — it can design its fab and its pricing purely around the 2027 target, rather than around a legacy roadmap.
Whether that translates into actual orders is still an open question. Rapidus has repeatedly said it is in discussions with prospective customers for 2nm capacity without naming any of them, and unlike TSMC or Samsung, it has no existing high-volume foundry relationships to lean on for early revenue. Industry analysts tracking the project have pointed to fabless AI accelerator and networking-chip designers — companies that need advanced nodes but have historically struggled to get priority allocation from TSMC — as the more plausible early customer base than smartphone or PC chip designers, who tend to demand higher-volume production Rapidus won't offer for years.
Hokkaido's supporting cast: power, water and people
Chitose was picked partly for reasons that have nothing to do with chip physics. The site sits near abundant hydroelectric and geothermal power, a Hokkaido advantage Rapidus and local officials have cited repeatedly as production scales toward the levels 2nm fabrication demands — a single leading-edge fab can draw as much electricity as a small city. New Chitose Airport, a short drive away, gives the site cargo capacity for importing lithography tools and exporting finished wafers. Local governments have also committed to expanding worker housing and transit around the plant, anticipating a workforce that Rapidus estimates will need to grow into the thousands as the line moves from pilot to mass production.
Staffing has proven harder than infrastructure. Japan's semiconductor engineering talent pool shrank considerably during the two decades after companies like Elpida and Renesas scaled back domestic chip investment, and Rapidus has had to recruit process engineers from South Korea, Taiwan and the United States alongside domestic hires, while running training partnerships with Hokkaido University and Chitose Institute of Science and Technology to rebuild a local pipeline. Some of those recruits previously worked at TSMC's own Kumamoto plant, a separate but geographically close project that has become an unplanned proving ground for the kind of advanced-node workforce Japan lost.
A test case for the rest of the region
Rapidus is the most visible piece of a broader Japanese effort to rebuild domestic chip capacity after decades of ceding ground to Taiwan and South Korea, alongside subsidies that helped bring TSMC's Kumamoto fab online and separate support for Kioxia's memory operations. Unlike those projects, Rapidus is attempting something no Japanese company has managed since the 1980s: building and operating a fab at the actual leading edge, not a generation or two behind it. The government's willingness to keep funding a company with no revenue and no track record reflects how much strategic weight Tokyo has put on the outcome — a successful Rapidus would give Japan, and by extension the US and allied semiconductor supply chains, a source of advanced logic capacity outside Taiwan for the first time in a generation.
The company has said it expects to demonstrate full risk production — wafers built at commercial-representative quality, even if not yet at commercial volume — before the end of 2026, with mass production targeted for 2027. Whether that timeline holds will depend less on the transistor technology itself, which IBM and imec have already validated in principle, than on whether a company running its first fab can push yields high enough, fast enough, to convince customers who have spent decades trusting TSMC and Samsung with their most advanced designs to bet on a newcomer instead.