Taiwan Semiconductor Manufacturing Company told investors on its July 17 earnings call that demand for CoWoS advanced packaging — the process that binds high-bandwidth memory to logic dies inside Nvidia's and AMD's flagship AI accelerators — now outstrips available capacity through at least mid-2027. Coming after months of investor questions about GPU allocation, the disclosure marks a shift in where the AI chip supply chain is actually constrained: not at the wafer-fabrication stage, but at the packaging step that turns finished silicon into a shippable accelerator.
CoWoS Lines Fully Booked Into 2027
Finance chief Wendell Huang said CoWoS-L and CoWoS-R output at the company's Chiayi facilities is running at full allocation, with the newer AP8 packaging building — commissioned earlier this year — already booked by customers through the first quarter of 2027. Also relying on CoWoS-L for their multi-die designs are Nvidia's Blackwell Ultra and the upcoming Vera Rubin platform, along with AMD's Instinct MI400 series, scheduled to ship in volume before the end of 2026. Because packaging capacity, rather than transistor supply, now sets the ceiling on shipments, customers who secured slots earliest hold a structural advantage over later entrants — a dynamic Huang described as unlikely to ease before new packaging buildings come fully online.
South Korea's Samsung Electronics operates a competing interposer-based packaging line, branded I-Cube, at its Hwaseong campus, but analysts tracking the sector say Samsung's advanced packaging output remains a fraction of TSMC's volume for GPU-class dies. That gap has left most large AI accelerator orders routed through Taiwan regardless of where the underlying logic wafer was originally fabricated.
Export Controls Widen Alongside the Expansion
Taiwan's Ministry of Economic Affairs confirmed this week that it has broadened export-licensing requirements to cover a wider category of packaging equipment, aligning with the US Commerce Department's April 2026 update restricting chipmaking tools destined for entities tied to Chinese state-backed foundries. After reports surfaced that SMIC and Huawei have accelerated in-house packaging research — including a chip-stacking approach domestic Chinese media have labeled CoWoP — Taiwan's move drew renewed attention from analysts tracking the mainland's efforts to close the gap. Independent teardown analysis cited by supply-chain researchers has not found the Chinese approach matching CoWoS-L's bandwidth density, though the gap has narrowed over the past two years. Meanwhile, TSMC is adding a third Chiayi packaging building, AP9, and converting part of a planned Taichung expansion from InFO lines to CoWoS capacity, according to a supplier filing reviewed by trade publication DigiTimes.
Separately, TSMC's Arizona fab has begun producing 4-nanometer wafers for Apple and Nvidia, but the company has disclosed no plans to build packaging capacity outside Taiwan. That leaves the CoWoS chokepoint — and the geopolitical exposure that comes with concentrating it on the island — set to persist well into 2027.