TSMC Confirms N2 Mass Production at Hsinchu Fab With Apple and AMD as First Customers

Taiwan Semiconductor Manufacturing Company confirmed on Tuesday that volume production of its 2-nanometre process node, marketed as N2, has begun at Fab 20 in Hsinchu Science Park. The announcement, made during a closed-door analyst briefing later confirmed in a regulatory filing, names Apple and Advanced Micro Devices as the first commercial customers and signals a meaningful shift in the global advanced-logic supply chain.

Chief Executive C.C. Wei told analysts that N2 wafer output will ramp from 12,000 wafers per month in May to roughly 80,000 by the end of the fourth quarter, with yields already exceeding internal targets at the equivalent stage of N3 introduction in late 2022. "We are confident in the trajectory. The defect density at this point of the ramp is the lowest we have ever achieved on a leading node," Wei said.

What N2 actually delivers

TSMC's N2 introduces gate-all-around (GAA) nanosheet transistors for the first time, replacing the FinFET architecture used since 16-nanometre. According to performance data shared with select customers, N2 delivers between 10 and 15 per cent higher performance at iso-power compared with N3E, or 25 to 30 per cent lower power at iso-frequency. Logic density improves by approximately 15 per cent.

The node uses 14 layers of extreme ultraviolet (EUV) lithography, three more than N3E, and introduces high-numerical-aperture EUV (high-NA EUV) for selective critical layers. ASML confirmed in its first-quarter earnings call that TSMC has taken delivery of four EXE:5000 high-NA tools, with two more scheduled for the third quarter.

Apple's A20 and M6 silicon

Apple is widely understood to be the lead-volume customer, with the A20 system-on-chip, expected in the iPhone 18 Pro line announced in September, becoming the first consumer device to ship on N2. Industry sources estimate Apple has booked approximately 60 per cent of TSMC's initial N2 capacity through the first half of 2027.

The company's M6 chip family for Mac and iPad will follow on a derivative N2P variant scheduled for early 2027. N2P is expected to introduce backside power delivery, marketed by TSMC as Super Power Rail, which improves power-delivery efficiency at the cost of additional process complexity.

AMD targets data-centre and AI markets

AMD's commitment to N2 covers two product families. The first is the EPYC Venice generation of server processors, which will tape out in the second half of 2026 with first silicon expected in mid-2027. The second is the Instinct MI450 series of AI accelerators, with which AMD is positioning to compete more directly against Nvidia's Rubin generation and Blackwell Ultra refreshes.

AMD Chief Executive Lisa Su, speaking at the Computex 2026 keynote in Taipei last week, said the MI450 will deliver "more than two times" the AI training performance per watt of the MI355X. The chip uses chiplets manufactured on N2 for compute dies and N3P for memory and IO dies, packaged with TSMC's CoWoS-L advanced substrate technology.

Other customers in the queue

• Nvidia: Confirmed at GTC 2026 that the Rubin Ultra generation, due in late 2027, will use N2 for compute dies.
• Qualcomm: Snapdragon 8 Gen 5 for Galaxy line scheduled for N2 production in Q1 2027.
• MediaTek: Dimensity 9500 flagship targeting late 2026 launch on N2.
• Broadcom: Custom AI ASICs for Google and Meta announced for 2027 on N2.
• Intel: Tile-level outsourcing for Panther Lake successor remains under negotiation.

Pricing and capacity politics

TSMC has set N2 wafer pricing at approximately $30,000 per 300mm wafer, up from roughly $20,000 for N3E and $16,000 for N5. The company is not offering volume discounts during the first eighteen months of production, a departure from prior nodes where early customers received pricing concessions in exchange for risk-sharing.

Industry analysts at TrendForce estimate TSMC will generate approximately $14 billion in N2-related revenue in 2026 and $38 billion in 2027, contributing roughly 18 per cent of total foundry revenue by the end of next year. Gross margins on N2 are expected to be dilutive in 2026 as depreciation and high-NA tool costs weigh on profitability, before recovering in 2027 as utilisation rises above 85 per cent.

Geographic diversification

While Hsinchu Fab 20 will remain the primary N2 site, TSMC has begun preparatory work for N2 capacity at Arizona Fab 21 Phase 3, with first equipment deliveries expected in the third quarter of 2027 and risk production in early 2028. The Japan Kumamoto site (JASM) and Germany Dresden site (ESMC) will not host N2 capacity in the current planning cycle, focusing instead on mature and specialty processes.

The Taiwanese government's Ministry of Economic Affairs reaffirmed last week that leading-edge nodes, defined as N2 and below, will remain subject to export-control reviews when produced outside Taiwan, with formal approval required for any capacity exceeding 30 per cent of domestic output.

Competitive positioning

The N2 ramp arrives as competing foundries struggle with their own GAA introductions. Samsung Foundry's SF2 process, which entered limited production in late 2025, has reported yields below 50 per cent on initial Exynos products, prompting Samsung System LSI to dual-source the upcoming Exynos 2600 with TSMC. Intel Foundry's 18A node entered production in the first quarter on Panther Lake, but external customer wins remain limited to Microsoft and a small set of defence-related programmes.

For TSMC, the N2 launch consolidates a leadership position that has widened over the past three nodes. The combination of process maturity, packaging integration through CoWoS and SoIC, and a customer base that now spans every major designer of leading-edge silicon makes N2 a defining commercial event for the global semiconductor industry in 2026.

The next milestone is the formal HVM declaration in TSMC's second-quarter earnings call on 17 July, where management is expected to disclose initial revenue contribution and updated capacity guidance for 2027.