Taiwan Semiconductor Manufacturing Company is scaling its 2-nanometre N2 process across five fabs in Hsinchu and Kaohsiung, with monthly wafer starts on track to approach 100,000 by the end of 2026. Following N2's move into volume production, the ramp marks the fastest simultaneous multi-fab rollout TSMC has attempted at this stage of any node, according to supply-chain trackers monitoring the buildout. The pace reflects the scale of AI and high-performance-computing demand now reaching the leading edge of the foundry business.
Wafer starts on N2 reached roughly 50,000 to 60,000 units a month through the first half of 2026, per estimates from supply-chain tracker SMBOM. By early in the fourth quarter, that figure is expected to climb past 80,000 and edge toward 100,000 by year-end, as the two Hsinchu lines and three Kaohsiung lines reach fuller utilisation. Longbridge Securities has pointed to a longer-term target near 140,000 wafers a month once the full five-fab network matures.
Kaohsiung's P1 fab alone was contributing about 10,000 wafers a month in the early phase of the ramp, with P1 and P2 combined reaching 30,000 to 35,000 wafers monthly by the close of 2025. By its own account, TSMC is targeting first-year N2 output roughly 45% higher than the equivalent first year of its 3-nanometre node, with 2nm capacity set to grow at a 70% compound annual rate between 2026 and 2028.
AMD and Fujitsu are the two customers TSMC has publicly disclosed for N2 so far. Also working through design qualification, according to supply-chain reports, are MediaTek and Qualcomm — though neither has confirmed a production commitment. Apple, historically TSMC's first customer on a new leading-edge process, has not been named in connection with N2 orders to date.
Pricing on the node reflects the tightness of the ramp. At roughly $30,000 apiece, N2 wafers carry a premium that sits well above the roughly $20,000 wafer cost Rapidus has cited for its own 2nm-class process, which the Japanese foundry is targeting for commercial launch in 2027. TSMC's leading-edge capacity, meanwhile, is already booked into 2028, according to industry pricing trackers, while Samsung's competing SF2 node has yet to disclose a comparable wafer price or a major fabless customer win.
The N2 ramp is running alongside a parallel expansion of TSMC's 3-nanometre lines, with monthly 3nm wafer starts reported to be climbing toward 180,000 by early in the fourth quarter across sites in Taiwan, Arizona and Japan. Separately, a follow-on 2nm process — N2P — is scheduled to enter production in the second half of 2026, offering density and power refinements on the same base architecture. TSMC's roadmap beyond N2 includes A16, a 1.6-nanometre-class node due in the fourth quarter of 2026 that introduces backside power delivery, followed by further nodes extending to A12 by 2029.