Qualcomm is enlisting Samsung Electronics and SK hynix as memory partners for its High-Bandwidth Compute (HBC) architecture, with TSMC expected to handle advanced packaging integration, according to a report by South Korean outlet The Elec cited by TrendForce on August 27, 2026.
Qualcomm unveiled HBC in June, an architecture that separates the compute engine, or XPU, from the system-on-chip and places it beneath a stacked LPDDR DRAM package. Through-silicon vias link the compute die directly to the memory stack above it, a design meant to avoid the cost structure of HBM and advanced packaging while still delivering high bandwidth and capacity.
Malladi Cites Direct Talks in South Korea
Speaking at the Deutsche Bank Technology Conference on August 26, Qualcomm executive vice president Durga Malladi said he met with both Korean memory makers in South Korea shortly after the company's Investor Day, according to a transcript published by Investing.com. Malladi said he expected pushback on HBC from Samsung and SK hynix. Instead, both companies responded positively and signaled willingness to deepen cooperation with Qualcomm.
The Elec reports that Samsung and SK hynix are now developing HBC alongside their existing HBM roadmaps, and that Qualcomm is working with both suppliers to secure stable DRAM supply as the architecture moves toward production. The role split described by The Elec assigns Qualcomm the core design work, system integration, the compute die and TSV design; Samsung and SK hynix are responsible for DRAM stacking; TSMC is expected to support technology integration and advanced packaging.
Bandwidth Claims and Rollout Timeline
Qualcomm has not disclosed HBC's actual bandwidth figure. The Elec reports that current AI accelerators offer combined HBM bandwidth of roughly 21 to 24 TB/s, and that HBC is claimed to deliver six times the bandwidth and token-throughput efficiency of HBM at the same power draw. The architecture is also said to reach up to eight times the token throughput of conventional GPU systems at equivalent power, with a lower total cost of ownership than SRAM despite SRAM's higher raw speed.
According to TechPowerUp, the rollout begins with the AI200 accelerator later this year, which uses LPDDR5X and provides 43 TB of RAM per rack. First-generation HBC is set to debut in the AI250 in 2027, delivering 18 times the bandwidth of the AI200. A second-generation version follows in the AI300 in 2028, claimed at 54 times the AI200's bandwidth.
Broader Push Into Memory
The HBC partnership places Qualcomm alongside a wider group of chipmakers moving into memory-adjacent architectures as AI accelerator demand strains HBM supply. Samsung and SK hynix already supply the bulk of the world's HBM output for Nvidia and AMD accelerators, and both companies have said memory capacity is sold out well into 2027 on separate industry reporting this year. TSMC's expected packaging role would extend a relationship the foundry already has with both Korean memory makers on CoWoS-based AI chip production.