For years the semiconductor race was told as a story about transistor size — 7 nanometres, then 5, then 3, with the next node always framed as the finish line. That framing is now incomplete. The hardest bottleneck in supplying AI accelerators is no longer how small the transistors are, but how the finished chips are stitched together. Advanced packaging, and specifically the technique TSMC calls CoWoS, has become the gate that everything else waits behind.
CoWoS stands for chip-on-wafer-on-substrate, a method that places multiple silicon dies and stacks of high-bandwidth memory side by side on a single interposer. An Nvidia data-centre GPU is not one piece of silicon but a package — logic die plus several HBM stacks — and the value sits as much in the assembly as in the transistors. When TSMC cannot package fast enough, the AI chip supply tightens regardless of how many wafers the foundry can print.
Why packaging became the chokepoint
The shift traces directly to the structure of AI hardware. Training large models is bound by memory bandwidth, which is why each generation of accelerator stacks more HBM closer to the logic. Putting that memory physically next to the processor requires a large silicon interposer and precise alignment, and the capacity to do this at scale is concentrated in a handful of facilities.
Three constraints compound the problem:
- Interposer supply, where the silicon-based interposers used in the highest-end packages are themselves fabricated on wafers, competing for the same scarce capacity.
- HBM availability, dominated by SK Hynix, Samsung and Micron, with HBM3E qualified into leading accelerators and HBM4 the next contested milestone.
- Thermal and yield limits — the bigger the package and the more dies it carries, the more a single defect can scrap an expensive assembly.
TSMC has repeatedly told investors it is expanding CoWoS capacity, with reported plans to roughly double output, yet demand from Nvidia, AMD and the hyperscalers building custom silicon has kept the line booked well ahead.
The contenders moving in
The concentration has drawn competitors. Samsung is pushing its own 2.5D and 3D packaging under the I-Cube and X-Cube names and pitching a turnkey offer that combines its foundry, its HBM and its packaging in one house. Intel has built Foveros and EMIB into the core of its manufacturing pitch, using an organic-bridge approach rather than a full silicon interposer for some designs, which can ease the interposer constraint.
Outsourced assembly and test firms are climbing the value chain as well. ASE, Amkor and others have invested in advanced packaging lines, partly to absorb overflow that the leading foundries cannot handle. Amkor's Arizona facility, tied to the broader push to build packaging capacity outside East Asia, reflects how governments now treat packaging as a strategic step rather than a back-end afterthought.
What it means for Korea, Taiwan and Japan
The geography of this contest runs through three economies. Taiwan holds the lead in interposer-based packaging through TSMC. Korea controls the memory that those packages depend on, which gives SK Hynix and Samsung leverage that the HBM4 transition will only sharpen. Japan is positioning around materials and the equipment that packaging lines need, alongside the Rapidus effort to re-enter leading-edge logic.
The equipment makers sit underneath all of it. Advanced packaging needs hybrid bonding tools, lithography for redistribution layers and inspection systems precise enough to catch defects in stacked dies, and the firms supplying those tools have seen packaging become a growth line rather than a niche. The node race is not over, but the question that now decides who can ship an AI accelerator this quarter is whether the package can be built — not whether the transistor can be shrunk.